Anti-Tamper Digital Clocks - An Overview
Anti-Tamper Digital Clocks - An Overview
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Resettable delay line segments between a resettable hold off line phase 210-one affiliated with a minimum hold off time along with a resettable delay line section 210-N connected with a optimum hold off time are Each and every connected to discretely escalating delay moments. The Assess circuit 240 is brought on with the clock CLK and makes use of the plurality of delayed monotone indicators to detect a clock fault.
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Resettable hold off line segments involving a resettable delay line section associated with a bare minimum hold off time in addition to a resettable hold off line phase associated with a optimum delay time are Each individual linked to discretely escalating hold off times. The Examine circuit is activated through the clock and employs the plurality of delayed monotone signals to detect a clock fault.
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Disclosed is a technique for detecting clock tampering. In the method a plurality of resettable delay line segments are presented. Resettable hold off line segments between a resettable delay line segment connected to a minimal delay time along with a resettable delay line phase associated with a maximum hold off time are Just about every affiliated with discretely increasing delay times.
38. The apparatus for detecting voltage tampering as described in declare 37, whereby the resettable hold off line segments are reset all through a reset time frame, wherein the reset time period is previous to the Appraise time period.
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